Showing posts with label 3D Transistors. Show all posts
Showing posts with label 3D Transistors. Show all posts
Intel® Package on Package (PoP) BGA Rework Video
Description :
Intel has developed the processes to remove and replace high density electronic components packaged in a Ball Grid Array, or BGA format. For Package-on-Package, or "PoP" devices, these guidelines include : developing the proper Thermal Reflow Profile
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Beat Intel, Get Your 14 nm Process Development Kit Now!
Description :
The industry’s first process development kit (PDK) for 14nm logic chips has been announced by Imec. This early-version PDK contains all elements for design assessment of the 14nm node through device compact models, parasitic extraction, design rules, parameterized cells (pcells), and basic logic cells.
It anticipates the introduction of a number of new technologies like the use of FinFET transistors, which have a larger drive per unit footprint and higher performance at low supply voltages compared to the traditional planar technologies. Evolutions of this PDK will gradually also introduce the use of high-mobility channel materials. The PDK includes elements of both immersion- and EUV lithography, opening the way for a gradual transition from 193nm immersion to EUV lithography.
Starting from the PDK a first test chip is now being designed. This chip, planned for the second half of 2012, will allow testing the device-, interconnect-, process- and litho assumptions, as well as performance and power of circuits implemented at the tight area budgets of the 14nm node.
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From Sand to Silicon: The Making of Intel Microprocessors
Description :
You know Intel as world-class top microprocessor company, but what do you know about the making of a chip? Our guest blogger, Rob Kelton from Intel’s Internal Employee Communications team, walks us through the making of the microprocessor, the brain "behind the magic" of your PC.
Microprocessors have been called the most complex manufactured product on earth, created through hundreds of steps in an ultra-clean environment. A few years ago we shared a picture story of chip manufacturing on 45-nanometer (nm) process technology and now we’d like to share an updated version that includes our 22 nm and Tri-gate transistor technology (not every single step, but most of the important ones).
Silicon is the second most abundant element in the earth’s crust. Common sand has a high percentage of silicon. Silicon - the starting material for computer chip - is a semiconductor, meaning that it can be readily turned into an excellent conductor or an insulator of electricity, by the introduction of minor amounts of impurities.
Melted Silicon
In order to be used for computer chips, silicon must be purified so there is less than one alien atom per billion. It is pulled from a melted state to form a solid which is a single, continuous and unbroken crystal lattice in the shape of a cylinder, known as an ingot.
A mono-crystal silicon ingot has a diameter of 300 millimeters (mm) and weighs about 100 kilograms (roughly 220 pounds).
Ingot Slicing
The ingot is cut into individual silicon discs called wafers. Each wafer has a diameter of 300mm and is about 1 mm thick. Wafers are polished until they have flawless, mirror-smooth surfaces. Intel buys manufacturing-ready wafers from its suppliers. Wafer sizes have increased over time, resulting in decreased costs per chip. When Intel began making chips, wafers were only 50mm in diameter. Today they are 300mm, and the industry has a plan to advance to 450mm.
Fabrication of chips on a wafer consists of hundreds of precisely controlled steps which result in a series of patterned layers of various materials one on top of another.
What follows is a sample of the most important steps in this complex process.
Applying Photo Resist (Wafer Level)
Photolithography is the process by which a specific pattern is imprinted on the wafer. It starts with the application of a liquid known as photoresist, which is evenly poured onto the wafer while it spins. It gets its name from the fact that it is sensitive to certain frequencies of light (“photo”) and is resistant to certain chemicals that will be used later to remove portions of a layer of material (“resist”).
Exposure
The photoresist is hardened, and portions of it are exposed to ultraviolet (UV) light, making it soluble. The exposure is done using masks that act like stencils, so only a specific pattern of photoresist becomes soluble. The mask has an image of the pattern that needs to go on the wafer, it is optically reduced by a lens, and the exposure tool steps and repeats across the wafer to form the same image a large number of times.
Resist Development
The soluble photoresist is removed by a chemical process, leaving a photoresist pattern determined by what was on the mask.
Ion Implantation
The wafer with patterned photoresist is bombarded with a beam of ions (positively or negatively charged atoms) which become embedded beneath the surface in the regions not covered by photoresist. This process is called doping, because impurities are introduced into the silicon.
This alters the conductive properties of the silicon (making it conductive or insulating, depending on the type of ion used) in selected locations. Here we show the creation of wells, which are regions within which transistors will be formed.
This alters the conductive properties of the silicon (making it conductive or insulating, depending on the type of ion used) in selected locations. Here we show the creation of wells, which are regions within which transistors will be formed.
Removing Photo Resist
After ion implantation, the photoresist is removed and the resulting wafer has a pattern of doped regions in which transistors will be formed.
Begin Transistor Formation
Here we zoom into a tiny part of the wafer, where a single transistor will be formed. The green region represents doped silicon.
Today’s wafers can have hundreds of billions of such regions which will house transistors.
Etch
In order to create a fin for a tri-gate transistor, a pattern of material called a hard mask (blue) is applied using the photolithography process just described. Then a chemical is applied to etch away unwanted silicon, leaving behind a fin with a layer of hard mask on top.
Removing Photoresist
The hard mask is chemically removed, leaving a tall, thin silicon fin which will contain the channel of a transistor.
Silicon Dioxide Gate Dielectric
Using a photolithography step, portions of the transistor are covered with photoresist and a thin silicon dioxide layer (red) is created by inserting the wafer in an oxygen-filled tube-furnace. This becomes a temporary gate dielectric.
Polysilicon Gate Electrode
Again using a photolithography step, a temporary layer of polycrystalline silicon (yellow) is created. This becomes a temporary gate electrode.
Insulator
In another oxidation step, a silicon dioxide layer is created over the entire wafer (red/transparent layer) to insulate this transistor from other elements.
Intel uses a “gate last” (also known as “replacement metal gate”) technique for creating transistor metal gates. This is done in order to avoid transistor stability problems which otherwise might arise as a result of some subsequent high temperature process steps.
Removal of Sacrificial Gate
Using a masking step, the temporary (sacrificial) gate electrode and gate dielectric are etched away. The actual gate will now be formed; because the first gate was removed, this procedure is known as “gate last”.
Applying High-k Dielectric
Individual molecular layers are applied to the surface of the wafer in a process called “atomic layer deposition”. The yellow layers shown here represent two of these. Using a photolithography step, the high-k material is etched away from the undesired areas such as above the transparent silicon dioxide.
Metal Gate
A metal gate electrode (blue) is formed over the wafer and, using a lithography step, removed from regions other than where the gate electrode is desired.
The combination of this and the high-k material (thin yellow layer) gives the transistor much better performance and reduced leakage than would be possible with a traditional silicon dioxide/polysilicon gate.
Ready Transistor
This transistor is close to being finished. Three holes have been etched into the insulation layer (red color) above the transistor. These three holes will be filled with copper or other material which will make up the connections to other transistors.
Electroplating
The wafers are put into a copper sulphate solution at this stage. The copper ions are deposited onto the transistor thru a process called electroplating. The copper ions travel from the positive terminal (anode) to the negative terminal (cathode) which is represented by the wafer.
After Electroplating
On the wafer surface, the copper ions settle as a thin layer of copper.
Polishing
The excess material is mechanically polished away to reveal a specific pattern of copper. Multiple metal layers are created to interconnect (think: wires) all the transistors on the chip in a specific configuration. How these connections have to be “wired” is determined by the architecture and design teams that develop the functionality of the respective processor (e.g. Intel® Core™ i5 Processor ).
While computer chips look extremely flat, they may actually have over 30 layers to form complex circuitry. A magnified view of a chip will show an intricate network of circuit lines and transistors that look like a futuristic, multi-layered highway system.
While computer chips look extremely flat, they may actually have over 30 layers to form complex circuitry. A magnified view of a chip will show an intricate network of circuit lines and transistors that look like a futuristic, multi-layered highway system.
After all the interconnect layers are formed, an array of solder bumps is put on each die. These are the electrical connections with which the chip will communicate with the outside world, through the package in which it is later inserted. (These bumps are not shown in the illustrations). When wafer processing is complete, the wafers are transferred from the fab to an assembly/test facility.
There, the individual die are tested while still on the wafer, then separated, and the ones that pass are packaged. Finally, a thorough test of the packaged part is conducted before the finished product is shipped.
Wafer Sort
This portion of a ready wafer is being put through a test. A tester steps across the wafer; leads from its head make contact on specific points on the top of the wafer and an electrical test is performed. Test patterns are fed into every single chip and the response from the chip is monitored and compared to “the right answer”.
Wafer Slicing
The wafer is cut into pieces (called die). The above wafer contains future Intel processors codenamed Ivy Bridge.
Selecting Die for Packaging
The die that responded with the right answer to the test patterns will be packaged.
Individual Die
Like this one, have been cut out in the previous step (singulation). The die shown here is Intel’s first 22nm microprocessor codenamed Ivy Bridge.
Packaging
The package substrate, the die and the heat spreader are put together to form a completed processor. The green substrate builds the electrical and mechanical interface for the processor to interact with the rest of the PC system. The silver heat spreader is a thermal interface which helps dissipate heat.
Processor
Completed processor (Ivy Bridge in this case). A microprocessor has been called the most complex manufactured product made by man.
In fact, it takes hundreds of steps - only the most important ones have been included in this picture story - in the world’s cleanest environment (a microprocessor fab).
Class Testing
During this final test the processor is thoroughly tested for functionality, performance and power.
Binning
Based on the test result of class testing, processors with equal capabilities are binned together in trays, ready for shipment to customers.
Retail Package
Manufactured and tested processors are shipped to system manufacturers in trays or to retail stores in a box (the box shown is actually the box of a 32nm product and not the actual box for our 22nm Ivy Bridge products).
BONUS: Here’s a PDF presentation of this article that you can share with family and friends. If you need a PowerPoint version for training purposes, contact Markus Weingartner. You can also find a video, photos, and other useful presentations of “The Making of a Chip” in Intel's Press Kit.
READ ALSO: Bringing 100Mbps Ethernet to the Future Car
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Micro-Engineering: Scientists of UNSW Have Built The World's Tiniest Nano-Transistor
Description :
Scientists have built the world's tiniest transistor by precisely positioning a single phosphorus atom in a silicon crystal. The nano device is an important step in the development of quantum computers – super-powerful devices that will use the weird quantum properties of atoms to perform calculations billions of times faster than today's computers.
Michelle Simmons, of the University of NSW (New South Wales), said single atom devices had only been made before by chance and their margin of error for placement of the atom was about 10 nanometres, which affected performance. Her team was the first to be able to manipulate individual atoms with "exquisite precision".
Using a technique involving a scanning tunnelling microscope, they were able to replace one silicon atom from a group of six with one phosphorus atom, achieving a placement accuracy of better than half a nanometre. "This device is perfect," Professor Simmons, director of the Australian Centre of Excellence for Quantum Computation and Communication Technology, said.
The single atom sits between two pairs of electrodes, one about 20 nanometres apart, the other about 100 nanometres apart. When voltages were applied across the electrodes, the nano device worked like a transistor, a device that can amplify and switch electronic signals.
The research is published today in the journal Nature Nanotechnology.
First developed in the 1950s, transistors revolutionised the electronics industry. Since then, miniaturisation has seen the number of transistors squeezed onto a circuit double about every two years – a trend known as Moore's law.
Professor Simmons said this led to the prediction that transistors would need to reach the single atom level by 2020. "So we decided 10 years ago to start this program to try and make single atom devices as fast as we could, and try and beat that law." This had now been achieved eight to ten years ahead of the industry's schedule, she said.
Last year, Professor Simmons was named NSW Scientist of the Year for her team's research.
About 15 to 20 years of research is needed before quantum computers become widely available.
Researchers at Purdue University in the US, the University of Melbourne and the Korea Institute of Science and Technology Information in Daejeon were also involved in the research.
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EIA : Electronics and Industrial Automation 2012
Description :
Visit the biggest industrial automation trade show in Ukraine – EIA : Electronics and Industrial Automation, which will be held on April 17 – 20 in Kyiv, KyivExpoPlaza venue (2b, Salyutna st.)
The RS Ukraine and YE International - two leading distributors of electronic and electromechanical components, measuring equipment and power supplies. Will represent a wide range of Electronics Components, Power & Connectors Electrical, Automation & Cables Mechanical Products & Tools, IT & Safety Equipment.
EIA : Electronics and Industrial Automation will be located in the Hall 1 of KyivExpoPlaza venue together with the biggest electrical, -engineering trade fair elcomUkraine and TechnoDrive – compressors, pumps, engines, pneumatics etc.
12000 of visitors are expected to the events.
Details :
- Location : Kyiv, Ukraine
- Venue : Kyiv Expo Plaza
- Posted by : RS Ukraine
- Start time : Tuesday, 17 April, 2012 - 09:00
- End time : Friday, 20 April, 2012 - 17:00
- Event type : Trade show
- Cost : Free
- Lanaguage : English
- Application : Industrial
- Email : rs@rsukraine.com.ua
- Contact number : +38 (044) 501-55-41
- Website : http://ua.rsdelivers.com
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3D Transistors and Microelectronics. New 3D chip transistor (SGT) may rich 50 GHz
Description :
A transistor is the fundamental building block of all electronic devices. A transistor can be defined as a device, which is used to amplify signals and power. Integrated circuits are used in making of chips inside electronic gadgets such as smart phones, laptops and so on.
Researchers in Purdue and Harvard Universities have created a new type of transistor that will make the Integrated circuits more compact. This transistor is made from another material other than silicon and as the name suggest, a 3-D structure is given to the device compared to the conventional flat chips. Nano wires are used in these transistors instead of silicon so they will be more compact and more efficient. The nano wires used are made from iridium gallium arsenide semiconductor.
Iridium-gallium-arsenide is replaced for silicon in this device. As they are elements from the 3rd and 5th group of the periodic table, they are collectively known as the III-V group semiconductors. These semiconductors are known to conduct electrons five times better than silicon. The mobility of this material is also known to be higher. All these characteristics have urged chip manufacturers to replace silicon with this semiconductor in the coming years.
The 3D transistor, also referred as tri-gate transistor, was made by a process termed ”top- down method” in which components of the transistor is etched. This method will gain huge acceptance as it is compatible with most of the industrial processes. In 2012, a new generation of integrated chips is believed to come into market in which transistors will be placed horizontally rather than vertically. This is the reason for the 3D effect posed by these transistors. Thus, this device is the world’s first 3D-gate-allround transistor.
The transistor consists of a gate by which rapid ON-OFF switching action is possible and helps in the direct flow of current. By the introduction of 3D transistors, it is estimated that this gate length will reduce from 45nm to 22 nm. The nano wires are coated with a dielectric, which acts as the gate. Further research is being conducted to reduce the gate length to 18 nm. The only option available is to make a thinner dielectric layer by a process called atomic deposition. A thinner dielectric layer offers greater speed, low voltage requirements and lower power consumption. The device has improved its clock speed to 20 GHz.
This experiment was funded by the National Science foundation and Semiconductor research group. The latest development in this field was the design of a “finFET or fin Field Effect Transistor” in which the device has a fin like structure other than the conventional flat design.
By the introduction of 3D transistors computers will become faster, cooler and smarter. Intel is planning to release processors made from 3D transistor integrated chips in 2012. These chips are expected to be 10 times faster than the ones used now and will be more compact.
It is heard that a Japanese company named “Unisantis” is working with the researchers of Singapore’s Institute of micro electronics to develop a new 3D transistor called the SGT (Surrounding Gate Transistor) which will increase the clocking speed of the computers from 20 GHz to 50 GHz. The companies claim processor clockspeeds could reach between 20GHz and 50GHz by using a 3-D structure that arranges components vertically, as opposed to the horizontal design of our forefathers. The device is dubbed the Surrounding Gate Transistor (SGT).
And just as the alarming appearance of a sphere confounds — and yes — frightens a resident of Flatland, so shall the eldrich machinations of this 3-D transistor do unto this Registerhack. But rest assured brighter minds are on the case.
The design work is headed by CTO of Unisantis Fujio Masuoka - a man credited with the invention of flash memory. He'll be joined by some 30 academics, engineers and scientists on the project.
According to Masuoko, SGT is a vertical silicon pillar surrounded by memory cells, electrical contacts and various other unnamed components (our guess: the screeching souls of the damned). The 3-D structure apparently reduces the distance that electrons travel, generates less heat and costs less to produce than existing chips.
"The SGT also allows further improvements in silicon-based semiconductors, in terms of transistor size and processing speed, for at least 30 more years before the theoretical limits are reached. Such improvements are necessary for new-generation IC chips to meet the computing power demanded by IT products and computing networks of ever-increasing functionality and complexity," said Masuoka.
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